Beyond SOI - The NOI nanotransistor -Simulations results and new challenges

  • Cătălin Pârvulescu  ,
  • Cristian Ravariu  ,

  • c 
    Elena Manea  , 

  • Florin Babarada  , 
  • Alina Popescu  
  • a,c,eNational Institute for Research and Development in Microtechnologies - IMT Bucharest, Romania
  • b, dPolitehnica" University of Bucharest, Faculty of Electronics, Dept. of Electronic Devices Circuits and Architectures, Str. Splaiul Independentei 313, Sect.6, 060042, Bucharest, Romania
Cite as
Pârvulescu C., Ravariu C., Manea E., Babarada F., Popescu A. (2018). Beyond SOI - The NOI nanotransistor -Simulations results and new challenges. Proceedings of the 30th European Modeling & Simulation Symposium (EMSS 2018), pp. 7-11. DOI: https://doi.org/10.46354/i3m.2018.emss.002

Abstract

For the beginning, this paper reconsiders the Nothing On Insulator transistor work principle. Then, some additional new studies are approached. Two directions are envisaged: (i) to change the source and drain composition or properties; (ii) to check if the vacuum from nanocavity can be replaced by oxide. The simulations proved excellent drain subthreshold slope of 45mV/dec for n- -V-p+ NOI variant. Oxide sub-2nm allows similar tunneling conduction as in nVn NOI variant. Comparisons with experimental picked points
from literature are available.

References

  1. Liu D.M., Datta S., 2015. Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect
    Transistors. IEEE Trans. Electron Devices, 59 (4), 902–909
  2. Koswatta S.O., Lundstrom M.S., Nikonov D.E., 2009. Performance Comparison Between p-i-n
    Tunneling Transistors and Conventional MOSFETs. IEEE Trans. Electron Devices, 56 (3), 456–465
  3. Han J., Meyyappan M., 2014. Introducing the vacuum transistor: a device made of Nothing. IEEE Spectrum, 46 (6), 25–29.
  4. Armstrong M., 2015. The quest for the ultimate vacuum tube, IEEE Spectrum, 47 (12), 29–35
  5. Han J., Oh J., Meyyappan M., 2012. Vacuum nanoelectronics: Back to the future? Gate insulated
    nanoscale vacuum channel transistor. Applied Physics Letter, 100 (213505), 1–4.
  6. Subramanian K., Kang W.P., Davidson J.L., 2008. A Monolithic Nanodiamond Lateral Field Emission Vacuum Transistor. IEEE Electron Device Letter, 29 (11), 1259-1261.
  7. Boucart K., Ionescu A.M., 2007. Double-gate tunnel FET with high-kappa gate dielectric. IEEE Trans. Electron Devices, 54 (7), 1725–1733.
  8. Ravariu C., 2010. The implementation methodology of the real effects in a NOI nanostructure aided by simulation and modelling. Elsevier Simulation Modeling Practice and Theory, 18, (9), 1274-1285.
  9. Ravariu C., Babarada F., 2011. Modeling and simulation of special shaped SOI materials for the
    nanodevices implementation. Hindawi Journal of Nanomaterials, 792759 (6), 1–11.
  10. Ravariu C., 2005. A NOI – nanotransistor. Proceedings of IEEE International Conference of
    Semiconductors, pp. 65–68, Oct. 11-14, Sinaia, (Europe, Romania).
  11. Ravariu C., 2017. Gate Swing Improving for the Nothing On Insulator Transistor in Weak
    Tunneling. IEEE Transactions on Nanotechnology, 16 (6), 1115–1121.
  12. Pretet J., Monfray S., Cristoloveanu S., Skotnicki T., 2004. Silicon-On-Nothing MOSFETs:
    performance, short channels effects and back gate coupling. IEEE Trans. Electron Devices, 51 (2), 240–245.
  13. Ravariu C., 2016. Deeper Insights of the Conduction Mechanisms in a Vacuum SOI Nanotransistor. IEEE Transactions on Electron Devices, 63 (8), 3278–3283.
  14. Ravariu C., 2014. Compact NOI Nano-Device Simulation. IEEE Transactions on Very Large
    Scale Integration (VLSI) Systems, 22 (8), 1841– 1844
  15. Basak R., Maiti B., Mallik A., 2015. Analytical model of gate leakage current through bilayer oxide stack in advanced MOSFET. Superlattices and Microstructures, 80 (1), 20–31.